This application is related to commonly-assigned application Ser. No. 07/705,597, filed May 24, 1991.
1. Field of the Invention
This invention relates to a semiconductor circuit device such as a memory, a photoelectric converting device, a signal processing device or the like adapted for use in various electronic appliances, a manufacturing method therefor, and a wiring forming method for a semiconductor circuit, and more particularly to a multi-layered wiring structure thereof.
2. Related Background Art
In recent years, the efforts for higher levels of integration have been directed toward the realization of miniaturized functional devices, such as the development of a MOS transistor with a submicron gate length.
For example, a MOS transistor of a gate length of 0.8 .mu.m occupies an area of ca. 20 .mu.m.sup.2, and is suitable for a high level of integration.
However the conventional structure has been unable to provide sufficiently satisfactory characteristics even if the functional devices such as MOS transistors or bipolar transistors are sufficiently miniaturized to allow a high level of integration. This has been considered to be due to drawbacks in the process of forming fine functional devices, and the emphasis in developments has therefore been given to improvements in the manufacturing process.
However, the detailed investigation of the device structure and the manufacturing process by the present inventors has revealed that a development in the wiring structure significantly improves the production yield, with improvement in the performance.
More specifically, the conventional structure explained in the following has been associated with the drawback that, in the multi-layered wiring structure, the area occupied by the aluminum wirings of the second and third layers and by the through-holes in the first and second layers is increased, which hinders the higher integration of the fine device elements and also hinders the decrease of the parasitic capacitances which lead to delays in signals.
FIG. 18 is a schematic cross-sectional view of a multi-layered wiring structure in such a conventional semiconductor circuit device. In a two-layered wiring structure, through-holes of only one kind are required in order to connect the wirings of the first (lower) layer with those of the second (upper) layer, but, in a wiring structure involving three or more layers, through-holes of another kind are also required in order to connect the wirings of the second and third (uppermost) layer.
Such multi-layered wiring structure also poses a problem that the step in the interlayer insulation film becomes larger in the upper layer side. Such step becomes even larger if, as shown in FIG. 18A, a step h2 of the lower layer side, formed by an insulation film 1 and a wiring 2, overlaps with another step h1 of the upper layer side, formed by another insulation film 3 and a wiring 4. Consequently it has been difficult to reduce the step height in the upper layer. The insulation film provided to cover such an increased step inevitably has a larger thickness in such stepped portion (step h1) than in the flat portion. If a through-hole 5 is formed in the insulation film of increased thickness with an ordinary photoresist mask 6, the etching proceeds in the lateral direction of the insulation film 3 but the bottom aperture area S2 of the through-hole 5 becomes smaller than the area S1 of the photoresist mask (for example S1=5.times.5 .mu.m.sup.2 ; S2=3.times.3 .mu.m.sup.2), so that the through-hole 5 becomes more difficult to open as the insulation film becomes thicker. In the conventional semiconductor device with multi-layered wirings, this problem has been avoided by designing the through-holes connecting the wirings of the (n+1)-th and (n+2)-th layers to be larger than those connecting the wirings of the (lower) n-th and (n+1)-th layers. In this manner the through-holes 5 can be formed with a suitable size between the wirings, so that the troubles in forming the connection resulting from the step or the increased film thickness can be prevented.
In FIG. 18B there are shown a semiconductor substrate 7, an insulation film 8, an Al wiring 9 of the first layer, a first interlayer insulation film 10, a first through-hole 11, an Al wiring 12 of the second layer, a second interlayer insulation film 13, a second through-hole 14, and an Al wiring 15 of the third layer.
In the illustrated structure it will be understood that the size l.sub.1 of the contact hole CH is exceeded by the size l.sub.2 of the first through-hole 11, which is in turn exceeded by that l.sub.3 of the second through-hole 14. Such structure is for example disclosed in the Japanese Laid-open Patent Sho 59-117236.
FIG. 19 is a schematic view showing a wiring forming method for obtaining another multi-layered wiring structure in the conventional semiconductor circuit device.
In FIG. 19 there are shown, as an example, the wirings connected to a MOS transistor.
On the top surface side of a semiconductor substrate 16 there are formed source and drain areas 7, and a gate electrode 19 is formed across a gate insulation film 18 on a channel area between said source and drain.
On such substrate 16, an insulation film 20 is formed for example by a CVD process, and apertures (contact holes) CH are formed by patterning, for electrical contact with said source and drain areas (FIG. 19A) . Subsequently aluminum is deposited for example by sputtering and patterned by wet etching into the form of desired wirings 21 (FIG. 19 B).
Then the interlayer insulation film 22 is formed for example by a CVD process, and the through-hole TH is opened by patterning (FIG. 19C). Aluminum is then again deposited for example by sputtering and patterned by wet etching into the form of desired wirings 21, and the protective layer 23 is formed thereon (FIG. 19D).
However, because of such multi-layered structure, the wirings impose a significant influence on the performance of the device, and such influence can no longer be avoided by mere selection of the form and material of the wirings in consideration of the problems in the manufacturing process, as in the conventional technical concept.
Particularly in a photoelectric converting device such as an area sensor, the aperture rate is an important parameter governing the device characteristics, so that a structure enabling a reduction in the area of wirings in the light receiving part is desired. Also a flatter surface of the device is an essential condition for achieving miniaturization and improved functions, since otherwise:
1. the diameter of the through-holes, and the width and thickness of the wirings, have to be increased further as the layers are piled up in the multi-layered wiring structure;
2. the uppermost protective layer may be cracked, thus leading to defects, if the device surface has a large step; and
3. if other films such as a color filter or an antireflective film are further superposed on the device surface, a fine patterning in such films becomes difficult of the device surface is not flat.
Also the requirements for the wiring itself have become far stricter than before. For example, in highly integrated devices such as 4M or 16M DRAM in which the gate length is 0.8 .mu.m or shorter, the aspect ratio (depth/diameter) of the via hole in which aluminum or other metals have to be deposited is 1.0 or larger, and the diameter of such via hole is also as small as 1.0 .mu.m or less. Thus there is required an aluminum deposition technology for a via hole of a large aspect ratio.
In the wirings formed by the procedure as shown in FIG. 19, a recessed RC is formed on the contact hole CH, and a recessed RT is formed on the through hole TH.
However such recesses are undesirable because they lead to a significantly stepped structure. Such recesses will deteriorate the production yield in the multi-layered wiring structure, and also generate noises from stray light, if applied to a photoelectric converting device.
Also since the filling of apertures and the film deposition on the insulation layer are conducted at the same time, the conventional film forming method gives rise to formation a gap as indicated by S in FIG. 20, drastically deteriorating the production yield of the semiconductor devices.
Furthermore aluminum patterning with wet etching results in a fluctuating profile of the wiring, due to a side etching effect.